Technical Field
The disclosure relates in generally related to a semiconductor device and method for fabricating the same, and more particularly to a device with a fin field-effect transistor (FinFET) and method for fabricating the same.
Description of the Related Art
As the evolution of semiconductor process, technology node has progressed into nanometer-scale phenomena, a semiconductor device with higher functional density is provided. However, the critical sizes and features dimension of the semiconductor device are simultaneously shrunk small enough to make it challenging to produce a semiconductor device with the advantages of higher functional density without deteriorating the device performance. For overcoming the challenge, a device with a three-dimension design, such as a FinFET, is provided.
A FinFET is typically made by steps as follows: A portion of a silicon layer disposed on a substrate is removed by an etch process to form a vertical fin protruding from a surface of the substrate. A gate structure is then provided covering on the top surface and the sidewalls of the vertical fin to form a channel in the vertical fin, thereby an active region expending form the top surface to the sidewalls of the vertical fin can be identified. A gate structure is then formed on the vertical fin. In addition, a strained source/drain may be formed in the region of the vertical fin adjacent to the gate structure by an optional epitaxial growth process of strained silicon/silicon-germanium (Si/SiGe) material in order to improve the carrier mobility of the FinFET.
Generally, a FinFET structure may comprise a plurality of FinFETs each of which has a vertical fin protruding from a surface of the substrate, a gap with a step height may occur between two adjacent vertical fins after the gate structures of the corresponding FinFETs are formed on the vertical fins, and the topography of the FinFET structure may get more uneven when the gate structures that are respectively formed on different vertical fins have different device pattern density. Thus dishing problems may not still remain even if a polarization process, such as a chemical mechanical polishing (CMP) process, has been carried out on the surface of the FinFET structure, and the performance and yield of the subsequent processes performed on the surface of the FinFET structure may be deteriorated due to the roughness and dishing. In order to resolve the problems, a plurality of dummy stacks may be formed on insulation structures, such as shallow trench isolation (STI), disposed between two adjacent gate structures at the stage of forming the gate structures to provide an even local pattern density as well as to mitigate the dishing problems.
However, this approach still has some drawbacks. Because the dummy stacks of the prior art and the gate structures are not formed at the same plane, the dishing problems seem inevitable due to the height difference between the dummy stacks and the gate structures, such that the FinFET structure may be defect resulted from the uneven force generated by the subsequent processes performed on the surface of the FinFET structure. Therefore, there is a need of providing an improved semiconductor device and method for fabricating the same to obviate the drawbacks encountered from the prior art.